The present invention relates to a semiconductor device and semiconductor memory device having a insulated gate field effect transistor.
The conventional MOS field effect transistor (herein after abbreviated as "MOSFET") will be explained referring to the drawings. A typical construction is shown in FIG. 22a with a plan layout, and a sectional construction in FIG. 22b with A-A' section.
This element is made by separating the active region 19 through formation of thick insulating film 21 around the active region 19, which is used as a channel and source/drain electrode, by forming the gate electrode 30 after the gate insulating film is formed on such active region 19, and by forming the source electrode 40 and drain electrode 50 by ion implantation method, using this gate electrode 30 as mask, in the course of self-alignment. When this device is integrated on the same substrate, the electrical separation will be made by separation of the active regions with the above insulating film 21 made of oxide film. In forming this oxide film, it is possible to have this portion covered by the oxide film to be kept in inactive condition, even if the operating voltage is applied to the gate, by maintaining adequate thickness of the oxide film when compared to the gate insulating film. In order to grow this oxide film, the oxidation is carried out normally in wet atmosphere, thereby growing the oxide film to an adequate film thickness. Such oxidation is called the field oxidation, and the grown oxide film the field oxide film. Hereinafter, the above terms will be used.
When the degree of integration is increased in the above element, for example, when the interval of the device shown with "x" in the drawing is shortened, there will arise problems, where it becomes easier for the electric current to flow underneath the field insulating film 21, shown by an arrow mark "a" in the drawing.
In order to eliminate such unnecessary electric current path, the SOI (Silicon On Insulator) substrate construction, where the insulating film 20 is laid underneath the channel, as shown in FIG. 23, had been considered.
With respect to the FET formed on this insulator, discussions were made in IEEE Electron Device Letters, vol. 9, No. 2, Feb. (1988), pp. 97-99.
This construction forms the transistor on the substrate 10, which has therein the silicon oxide layer formed by ion implantation of oxygen, as the insulating layer 20. The transistor is made by such process that the gate insulating film is formed on the semiconductor of the surface of the above substrate and the gate electrode 30 is deposited, and thereafter the source electrode 40 and drain electrode 50 are formed in using ion implantation method to the gate portion, in the course of self-alignment . This transistor adopts the same construction as the construction of the normal MOSFET shown in FIG. 22a in a plan layout.
Further, as a feature of the construction which can be seen here, it can be mentioned that the silicon on the insulating film 20 has the thin film thickness d, namely the channel thickness, of at most approximately 0.1 .mu.m. With the construction shown in FIG. 22a and FIG. 22b, it is difficult for the field effect to reach the substrate interior at a distance from the gate. Whereas, with the construction shown in FIG. 23, the region where it is difficult for the field effect to reach is replaced by an insulator, thereby permitting effective control of the device action by the gate.
In the construction according to the above conventional techniques, there is the following relationship between the electric current I sent through the device and the channel width W: EQU I.varies.W
Therefore, there is a problem, where when W is reduced, I will also be reduced. Accordingly, it was not possible to reduce the plane dimensions without reducing the current.
This also constituted the restrictions, where plane dimensions could not be reduced in a semiconductor memory device formed by combining semiconductor devices according to the above conventional techniques (for example, SRAM) and in a semiconductor memory device formed by the combination of the semiconductor devices according to the above conventional techniques and the capacity elements, which are other semiconductor elements (for example, DRAM).